This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
A conventional computer system typically includes one or more central processing units (CPUs) and one or more memory subsystems. Computer systems also include peripheral devices for inputting and outputting data. Some common peripheral devices include, for example, monitors, keyboards, printers, modems, hard disk drives, floppy disk drives, and network controllers.
One of the important factors in the performance of a computer system is the speed at which the CPU operates. Generally, the faster the CPU operates, the faster the computer system can complete a designated task. One method of increasing the speed of a computer is using multiple CPUs, commonly known as multiprocessing. However, the addition of a faster CPU or additional CPUs can result in different increases in performance among different computer systems. Although it is the CPU that executes the algorithms required for performing a designated task, in many cases it is the peripherals that are responsible for providing data to the CPU and storing or outputting the processed data from the CPU. When a CPU attempts to read or write to a peripheral, the CPU often “sets aside” the algorithm that is currently executing and diverts to executing the read/write transaction (also referred to as an input/output transaction or an I/O transaction) for the peripheral. As can be appreciated by those skilled in the art, the length of time that the CPU is diverted is typically dependent on the efficiency of the I/O transaction.
Although a faster CPU may accelerate the execution of an algorithm, a slow or inefficient I/O transaction process associated therewith can create a bottleneck in the overall performance of the computer system. As the CPU becomes faster, the amount of time executing algorithms becomes less of a limiting factor compared to the time expended in performing an I/O transaction. Accordingly, the improvement in the performance of the computer system that could theoretically result from the use of a faster CPU or the addition of additional CPUs may become substantially curtailed by the bottleneck created by the I/O transactions. Moreover, it can be readily appreciated that any performance degradation due to such I/O bottlenecks in a single computer system may have a stifling effect on the overall performance of a computer network in which the computer system is disposed.
As CPUs have increased in speed, the logic controlling I/O transactions has evolved to accommodate these transactions. Thus, most I/O transactions within a computer system are now largely controlled by application specific integrated circuits (ASIC). These ASICs contain specific logic to perform defined functions. For example, Peripheral Component Interconnect (PCI) logic is instilled within buses and bridges, which govern I/O transactions between peripheral devices and the CPU. Today, PCI logic has evolved into the Peripheral Component Interconnect Extended (PCI-X) logic to form the architectural backbone of the computer system. PCI-X logic has features that improve upon the efficiency of communication between peripheral devices and the CPU. For instance, PCI-X technology increases bus capacity to more than eight times the conventional PCI bus bandwidth. For example, a 133 MB/s system with a 32 bit PCI bus running at 33 MHz is increased to a 1066 MB/s system with the 64 bit PCI bus running at 133 MHz.
An important feature of the new PCI-X logic is that it can provide backward compatibility with PCI enabled devices at both the adapter and system levels. Backward compatibility allows PCI controlled devices to operate with PCI-X logic. Although the devices will operate at the slower PCI speed and according to PCI specifications, the devices may be compatible to the new logic governing PCI-X transactions.
PCI-X logic provides an attribute phase that uses a 36-bit attribute field which describes bus transactions in more detail than the conventional PCI bus logic. This field includes information about the size of the transaction, the ordering of transactions, and the identity of the transaction initiator. Furthermore, the attribute field in the PCI-X standard incorporates the transaction byte count, which allows the bridge to determine exactly how much data to fetch from the memory.
PCI and PCI-X modes have different external bus timing requirements, and efforts to meet timing in one mode has a detrimental effect on the other mode. Typically, PCI mode specifications require devices operating in PCI mode to promote transactions in an asynchronous path from the input signal to an output register. Alternatively, the PCI-X specification does not facilitate an asynchronous functional path. Bridges within a computer system typically have one pathway that governs PCI and PCI-X transactions. However, because the two modes have differing timing approaches, a common pathway may cause timing problems. For example, a PCI transaction may transmit inaccurate data because the transaction is transmitted in a pathway common to both modes. These types of problems generally arise because of the different setup time and output time specified for each mode. For example, PCI 66 Mhz has an input setup time of 3 ns and a clock-to-output time of 6 ns, while PCI-X 100/133 Mhz has input setup time of 1.2 ns and a clock-to-output time of 3.8 ns.
The present invention may address one or more of the problems discussed above.